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GLVLSI
1999
IEEE
105views VLSI» more  GLVLSI 1999»
15 years 11 months ago
Area-Efficient Area Pad Design for High Pin-Count Chips
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...
Louis Luh, John Choma Jr., Jeffrey T. Draper
TACAS
1998
Springer
98views Algorithms» more  TACAS 1998»
15 years 11 months ago
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
Miroslav N. Velev, Randal E. Bryant
CASES
2006
ACM
15 years 10 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
FPL
2006
Springer
147views Hardware» more  FPL 2006»
15 years 10 months ago
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
TVLSI
2010
15 years 1 months ago
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang