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ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
16 years 3 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
15 years 11 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
ASPDAC
2009
ACM
190views Hardware» more  ASPDAC 2009»
15 years 10 months ago
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
AAAI
2010
15 years 8 months ago
Efficient Spectral Feature Selection with Minimum Redundancy
Spectral feature selection identifies relevant features by measuring their capability of preserving sample similarity. It provides a powerful framework for both supervised and uns...
Zheng Zhao, Lei Wang, Huan Liu
VCIP
2000
127views Communications» more  VCIP 2000»
15 years 8 months ago
Three-dimensional shape-adaptive discrete wavelet transforms for efficient object-based video coding
In this paper, we present an object-based coding scheme using three-dimensional shape-adaptive discrete wavelet transforms (SA-DWT). Rather than straightforward extension of 2D SA...
Jizheng Xu, Shipeng Li, Ya-Qin Zhang