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189
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VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 7 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
VLSID
2002
IEEE
128views VLSI» more  VLSID 2002»
16 years 7 months ago
System-Level Point-to-Point Communication Synthesis using Floorplanning Information
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...
Jingcao Hu, Yangdong Deng, Radu Marculescu
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
16 years 7 months ago
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
286
Voted
POPL
2008
ACM
16 years 7 months ago
Lightweight semiformal time complexity analysis for purely functional data structures
Okasaki and others have demonstrated how purely functional data structures that are efficient even in the presence of persistence can be constructed. To achieve good time bounds e...
Nils Anders Danielsson
POPL
2007
ACM
16 years 7 months ago
Interprocedural analysis of asynchronous programs
An asynchronous program is one that contains procedure calls which are not immediately executed from the callsite, but stored and "dispatched" in a non-deterministic ord...
Ranjit Jhala, Rupak Majumdar
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