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VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
16 years 7 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 7 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
16 years 7 months ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
16 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
16 years 7 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
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