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CHI
2005
ACM
16 years 7 months ago
Flexible timeline user interface using constraints
Authoring tools routinely include a timeline representation to allow the author to specify the sequence of animations and interactions. However, traditional static timelines are b...
Kazutaka Kurihara, David Vronay, Takeo Igarashi
VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
16 years 7 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 7 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
16 years 7 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
16 years 7 months ago
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
Sanjukta Bhanja, N. Ranganathan