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VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
16 years 7 months ago
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
Sanjukta Bhanja, N. Ranganathan
172
Voted
VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
16 years 7 months ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
HPCA
2005
IEEE
16 years 7 months ago
A Unified Compressed Memory Hierarchy
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
Erik G. Hallnor, Steven K. Reinhardt
RECOMB
2003
Springer
16 years 7 months ago
Combining phylogenetic and hidden Markov models in biosequence analysis
A few models have appeared in recent years that consider not only the way substitutions occur through evolutionary history at each site of a genome, but also the way the process c...
Adam C. Siepel, David Haussler
ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
16 years 3 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...