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VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
16 years 7 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
VLSID
2004
IEEE
181views VLSI» more  VLSID 2004»
16 years 7 months ago
Real Time Dynamic Voltage Scaling For Embedded Systems
This paper presents a very efficient and versatile method to handle Dynamic Voltage Scaling for minimizing energy consumption in an embedded system processor while maintaining rea...
Venkat Rao, Gaurav Singhal, Anshul Kumar
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
16 years 7 months ago
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
Weidong Wang, Anand Raghunathan, Niraj K. Jha
CHI
2001
ACM
16 years 7 months ago
Accordion summarization for end-game browsing on PDAs and cellular phones
We demonstrate a new browsing technique for devices with small displays such as PDAs or cellular phones. We concentrate on end-game browsing, where the user is close to or on the ...
Orkut Buyukkokten, Hector Garcia-Molina, Andreas P...
CADE
2004
Springer
16 years 7 months ago
Model Checking Using Tabled Rewriting
LRR [3] is a rewriting system developed at the Computer Science Department of University of Houston. LRR has two subsystems: Smaran (for tabled rewriting), and TGR (for untabled re...
Zhiyao Liang