5493 search results - page 676 / 1099 » Effectively Polynomial Simulations |
179
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ISQED
2007
IEEE
16 years 1 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
191
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ICDCS
2005
IEEE
16 years 15 days ago
2005
IEEE
Power heterogeneous ad hoc networks are characterized by link layer asymmetry: the ability of lower power nodes to receive transmissions from higher power nodes but not vice versa...
173
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ISPASS
2005
IEEE
16 years 14 days ago
2005
IEEE
Communication misses--those serviced by dirty data in remote caches--are a pressing performance limiter in shared-memory multiprocessors. Recent research has indicated that tempor...
204
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PPOPP
2005
ACM
16 years 13 days ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
231
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GECCO
2004
Springer
16 years 8 days ago
2004
Springer
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...