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ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
16 years 14 days ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda
COMSWARE
2007
IEEE
16 years 12 days ago
On Optimal Performance in Mobile Ad hoc Networks
In this paper we are concerned with finding the maximum throughput that a mobile ad hoc network can support. Even when nodes are stationary, the problem of determining the capaci...
Tapas K. Patra, Joy Kuri, Pavan Nuggehalli
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
16 years 10 days ago
Performance pathologies in hardware transactional memory
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Y...
HASE
2007
IEEE
16 years 9 days ago
Simulation Models and Implementation of a Simulator for the Performability Analysis of Electric Power Systems Considering Interd
Electric Power Systems (EPS) become more and more critical for our society, since they provide vital services for the human activities. At the same time, obtaining dependable beha...
Francesco Romani, Silvano Chiaradonna, Felicita Di...
CCS
2007
ACM
16 years 7 days ago
SecureBus: towards application-transparent trusted computing with mandatory access control
The increasing number of software-based attacks has attracted substantial efforts to prevent applications from malicious interference. For example, Trusted Computing (TC) technolo...
Xinwen Zhang, Michael J. Covington, Songqing Chen,...