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DATE
2006
IEEE
113views Hardware» more  DATE 2006»
16 years 19 days ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
GLOBECOM
2006
IEEE
16 years 19 days ago
Mobility Modeling and Handoff Analysis for IP/MPLS-Based Cellular Networks
Abstract— One of the major challenges for the wireless networks is related to efficient mobility management issue. In this paper, we propose a new micro-mobility management sche...
Rami Langar, Nizar Bouabdallah, Samir Tohmé...
IPPS
2006
IEEE
16 years 18 days ago
MT-ClustalW: multithreading multiple sequence alignment
ClustalW is the most widely used tool for aligning multiple protein or nucleotide sequences. The alignment is achieved via three stages: pairwise alignment, guide tree generation ...
K. Chaichoompu, Surin Kittitornkun, Sissades Tongs...
LCN
2006
IEEE
16 years 18 days ago
Optimal Multi-hop Cellular Architecture for Wireless Communications
Multi-hop relaying is an important concept in future generation wireless networks. It can address the inherent problems of limited capacity and coverage in cellular networks. Howe...
Yik Hung Tam, Hossam S. Hassanein, Selim G. Akl, R...
ACSC
2005
IEEE
16 years 6 days ago
Interprocedural Side-Effect Analysis and Optimisation in the Presence of Dynamic Class Loading
We introduce a new approach to computing interprocedural modification side effects for Java programs in the presence of dynamic class loading. When compile-time unknown classes c...
Phung Hua Nguyen, Jingling Xue