Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred ...
There is currently a huge gap between the two main technologies used to implement custom digital integrated circuit (IC) designs. At one end of the spectrum are field programmable...