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ASYNC
2000
IEEE
181views Hardware» more  ASYNC 2000»
15 years 11 months ago
Asynchronous Design Using Commercial HDL Synthesis Tools
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
Michiel M. Ligthart, Karl Fant, Ross Smith, Alexan...
CGI
2000
IEEE
15 years 11 months ago
SQUEEZE: Fast and Progressive Decompression of Triangle Meshes
An ideal triangle mesh compression technology would simultaneously support the following three objectives: (1) progressive refinements of the received mesh during decompression, (...
Renato Pajarola, Jarek Rossignac
FCCM
2000
IEEE
148views VLSI» more  FCCM 2000»
15 years 11 months ago
An Adaptive Cryptographic Engine for IPSec Architectures
Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectu...
Andreas Dandalis, Viktor K. Prasanna, José ...
185
Voted
IJCNN
2000
IEEE
15 years 11 months ago
Simulation of a Digital Neuro-Chip for Spiking Neural Networks
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
Tim Schönauer, S. Atasoy, N. Mehrtash, Heinri...
INFOCOM
2000
IEEE
15 years 11 months ago
Management of Advanced Services in H.323 Internet Protocol Telephony
The Intelligent Network (IN) represents the world wide accepted basis for uniform provisioning of advanced telecom services. On the other hand IP based communication is fast becomi...
Bernard Pagurek, Jinrong Tang, Tony White, Roch H....