This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
Context-aware Web services are currently emerging as an important technology for building innovative contextaware applications. Unfortunately, context-aware Web services are still...
Quan Z. Sheng, Sam Pohlenz, Jian Yu, Hoi S. Wong, ...
For my dissertation, I am designing, implementing and evaluating the use of a new kind of "authorable" virtual peer that allows children with autism to learn about recip...
In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices ...