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ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
16 years 9 days ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
FPL
2004
Springer
103views Hardware» more  FPL 2004»
16 years 3 days ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...
ARITH
2003
IEEE
16 years 1 days ago
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge
In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we descri...
Sorin Cotofana, Casper Lageweg, Stamatis Vassiliad...
INFOCOM
2000
IEEE
15 years 11 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin
MSE
2000
IEEE
118views Hardware» more  MSE 2000»
15 years 11 months ago
MPEG Video Streaming with VCR Functionality
—With the proliferation of online multimedia content, the popularity of multimedia streaming technology, and the establishment of MPEG video coding standards, it is important to ...
Chia-Wen Lin, Jeongnam Youn, Jian Zhou, Ming-Ting ...