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ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
16 years 14 days ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
IPPS
2005
IEEE
15 years 11 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
CL
2000
Springer
15 years 10 months ago
Modelling Digital Circuits Problems with Set Constraints
A number of diagnostic and optimisation problems in Electronics Computer Aided Design have usually been handled either by specific tools or by mapping them into a general problem s...
Francisco Azevedo, Pedro Barahona
COORDINATION
2000
Springer
15 years 10 months ago
An Agent Mediated Approach to Dynamic Change in Coordination Policies
Distributed information systems for decision-support, logistics, and e-commerce involve coordination of autonomous information resources and clients according to specific domain in...
Prasanta K. Bose, Mark G. Matthews
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
14 years 10 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas