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DATE
2009
IEEE
124views Hardware» more  DATE 2009»
16 years 1 months ago
Design and implementation of scalable, transparent threads for multi-core media processor
—In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the num...
Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyosh...
DATE
2009
IEEE
180views Hardware» more  DATE 2009»
16 years 1 months ago
FSAF: File system aware flash translation layer for NAND Flash Memories
NAND Flash Memories require Garbage Collection (GC) and Wear Leveling (WL) operations to be carried out by Flash Translation Layers (FTLs) that oversee flash management. Owing to ...
Sai Krishna Mylavarapu, Siddharth Choudhuri, Avira...
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
16 years 1 months ago
System-level hardware-based protection of memories against soft-errors
We present a hardware-based approach to improve the resilience of a computer system against the errors occurred in the main memory with the help of error detecting and correcting ...
Valentin Gherman, Samuel Evain, Mickael Cartron, N...
EUROMICRO
2009
IEEE
16 years 1 months ago
Foundations for a Model-Driven Integration of Business Services in a Safety-Critical Application Domain
—Current architectures for systems integration provide means for forming agile business processes by manually or dynamically configuring the components. However, a major challeng...
Richard Mordinyi, Thomas Moser, eva Kühn, Ste...
GLOBECOM
2009
IEEE
16 years 1 months ago
Development Framework for Implementing FPGA-Based Cognitive Network Nodes
—This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture ware abstraction, an adaptive run-time system for managing co...
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris...