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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
16 years 8 days ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
ISCA
2005
IEEE
154views Hardware» more  ISCA 2005»
16 years 8 days ago
Temporal Streaming of Shared Memory
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Tempor...
Thomas F. Wenisch, Stephen Somogyi, Nikolaos Harda...
161
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ISM
2005
IEEE
74views Multimedia» more  ISM 2005»
16 years 8 days ago
Striping Delay-sensitive Packets over Multiple Burst-loss Channels with Random Delays
Multi-homed mobile devices have multiple wireless communication interfaces, each connecting to the Internet via a long range but low speed and bursty WAN link such as a cellular l...
Gene Cheung, Puneet Sharma, Sung-Ju Lee
ISORC
2005
IEEE
16 years 8 days ago
Placement Solutions for Multiple Versions of A Multimedia Object
Transcoding is an important technology which adapts the same multimedia object to diverse mobile appliances; thus, users’ requests for a specified version of a multimedia objec...
Keqiu Li, Hong Shen, Francis Y. L. Chin
ISPDC
2005
IEEE
16 years 8 days ago
A Distributed Prime Sieving Algorithm based on Scheduling by Multiple Edge Reversal
Abstract— In this article, we propose a fully distributed algorithm for finding all primes in an given interval [2..n] (or (L, R), more generally), based on the SMER — Schedul...
Gabriel Paillard, Christian Antoine Louis Lavault,...
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