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FMCAD
2007
Springer
15 years 10 months ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet
FMCAD
2009
Springer
15 years 10 months ago
Industrial strength refinement checking
This paper discusses a methodology used on an industrial hardware development project to validate various cache-coherence protocol components. The idea is to use a high level model...
Jesse D. Bingham, John Erickson, Gaurav Singh, Fle...
HRI
2007
ACM
15 years 10 months ago
Developing performance metrics for the supervisory control of multiple robots
Efforts are underway to make it possible for a single operator to effectively control multiple robots. In these high workload situations, many questions arise including how many r...
Jacob W. Crandall, M. L. Cummings
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
15 years 10 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad
GLVLSI
2009
IEEE
151views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Reliability aware NoC router architecture using input channel buffer sharing
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Mohammad Hossein Neishaburi, Zeljko Zilic
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