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INFOCOM
2003
IEEE
15 years 11 months ago
Measuring Bottleneck Bandwidth of Targeted Path Segments
Abstract— Accurate measurement of network bandwidth is crucial for network management applications as well as flexible Internet applications and protocols which actively manage ...
Khaled Harfoush, Azer Bestavros, John W. Byers
MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
15 years 11 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 11 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
CASES
2003
ACM
15 years 11 months ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan