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ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 10 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
CIAC
1994
Springer
148views Algorithms» more  CIAC 1994»
15 years 10 months ago
Efficient Reorganization of Binary Search Trees
We consider the problem of maintaining a binary search tree (BST) that minimizes the average access cost needed to satisfy randomly generated requests. We analyze scenarios in whi...
Micha Hofri, Hadas Shachnai
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
15 years 10 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
DAC
2010
ACM
15 years 10 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
DAC
2010
ACM
15 years 10 months ago
An efficient phase detector connection structure for the skew synchronization system
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...
Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih...