Sciweavers

5230 search results - page 806 / 1046
» Dynamic Optimality -- Almost
Sort
View
ICPP
2003
IEEE
15 years 12 months ago
Procedural Level Address Offset Assignment of DSP Applications with Loops
Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions an...
Youtao Zhang, Jun Yang 0002
ICRA
2003
IEEE
125views Robotics» more  ICRA 2003»
15 years 12 months ago
Online footstep planning for humanoid robots
We present an online algorithm for planning sequences of footstep locations that encode goal-directed navigation strategies for humanoid robots. Planning footsteps is more general...
James J. Kuffner Jr., Satoshi Kagami, Koichi Nishi...
INFOCOM
2003
IEEE
15 years 12 months ago
Measuring Bottleneck Bandwidth of Targeted Path Segments
Abstract— Accurate measurement of network bandwidth is crucial for network management applications as well as flexible Internet applications and protocols which actively manage ...
Khaled Harfoush, Azer Bestavros, John W. Byers
MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
15 years 12 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 12 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...