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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
ATAL
2008
Springer
15 years 8 months ago
A statistical relational model for trust learning
We address the learning of trust based on past observations and context information. We argue that from the truster's point of view trust is best expressed as one of several ...
Achim Rettinger, Matthias Nickles, Volker Tresp
TC
2008
15 years 6 months ago
Counter-Based Cache Replacement and Bypassing Algorithms
Recent studies have shown that, in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Mazen Kharbutli, Yan Solihin
RTS
2008
119views more  RTS 2008»
15 years 5 months ago
Symbolic quality control for multimedia applications
We present a fine grain quality control method for multimedia applications. The method takes as input an application software composed of actions. The execution times of actions a...
Jacques Combaz, Jean-Claude Fernandez, Joseph Sifa...