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ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
16 years 3 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 12 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
ISLPED
1996
ACM
83views Hardware» more  ISLPED 1996»
15 years 10 months ago
12-b 125 MSPS CMOS D/A designed for spectral performance
A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 ...
Douglas Mercer, Larry Singer
ICC
2008
IEEE
135views Communications» more  ICC 2008»
16 years 1 months ago
Using Soft-Line Recursive Response to Improve Query Aggregation in Wireless Sensor Networks
— In large Wireless Sensor Networks (WSNs), each hop might incur varying delays due to medium access contention, transmission and computation delays. Fast and efficient query re...
Xiaoming Lu, Matt Spear, Karl N. Levitt, Norman S....
CODES
2005
IEEE
16 years 7 days ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...