Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 ...
— In large Wireless Sensor Networks (WSNs), each hop might incur varying delays due to medium access contention, transmission and computation delays. Fast and efficient query re...
Xiaoming Lu, Matt Spear, Karl N. Levitt, Norman S....
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...