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HPCA
2005
IEEE
16 years 6 days ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
CONCURRENCY
2010
104views more  CONCURRENCY 2010»
15 years 6 months ago
Performance analysis of an experimental wireless relay sensor network
Communication through relay channels in wireless sensor networks can create diversity and consequently improve robustness of data transmission for ubiquitous computing and network...
Gu-Chun Zhang, Xiao-Hong Peng, Xuan-Ye Gu
DATE
2002
IEEE
124views Hardware» more  DATE 2002»
15 years 11 months ago
Crosstalk Alleviation for Dynamic PLAs
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
SECON
2007
IEEE
16 years 26 days ago
Self-Learning Repeated Game Framework for Distributed Primary-Prioritized Dynamic Spectrum Access
Dynamic spectrum access has become a promising approach to fully utilize the scarce spectrum resources. In a dynamically changing spectrum environment, it is very important to desi...
Beibei Wang, Zhu Ji, K. J. Ray Liu
ICETET
2009
IEEE
15 years 4 months ago
High Performance WDM Using Semiconductor Tunable Laser
Advances in optical networking have lead to the explosive growth of communication network. Telecom applications began to drive significant investments into this field to support t...
S. S. Agrawal, K. D. Kulat, M. B. Daigavane