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SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
15 years 12 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
CAL
2007
15 years 6 months ago
Explaining Dynamic Cache Partitioning Speed Ups
Abstract— Cache Partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is im...
Miquel Moretó, Francisco J. Cazorla, Alex R...
ICAS
2005
IEEE
134views Robotics» more  ICAS 2005»
16 years 1 days ago
Timing Performance Control in Web Server Systems Utilizing Server Internal State Information
How to effectively allocate system resource to meet the Service Level Agreement (SLA) of Web servers is a challenging problem. In this paper, we propose an improved scheme for aut...
Xue Liu, Rong Zheng, Jin Heo, Qixin Wang, Lui Sha
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
15 years 10 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
GI
2001
Springer
15 years 11 months ago
Improving Goodput by Relaying in Transmission-Power-Limited Wireless Systems
In wireless communication systems, the capacity of a cell (the amount of correctly delivered traffic in unit time) is a precious resource that can not be arbitrarily increased. T...
Seble Mengesha, Holger Karl, Adam Wolisz