4725 search results - page 837 / 945 » Dynamic Architecture Extraction |
181
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NOCS
2007
IEEE
16 years 19 days ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
282
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ICDE
2009
IEEE
16 years 8 months ago
2009
IEEE
In recent years, the sketch-based technique has been presented as an effective method for counting stream items on processors with limited storage and processing capabilities, such...
142
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
193
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
157
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...