4725 search results - page 759 / 945 » Dynamic Architecture Extraction |
220
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HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
177
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HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
Chip-multiprocessors are becoming the dominant vehicle for general-purpose processing, and parallel software will be needed to effectively utilize them. This parallel software is ...
203
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
191
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HPCA
2003
IEEE
16 years 6 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
167
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HPCA
2002
IEEE
16 years 6 months ago
2002
IEEE
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...