Sciweavers

4725 search results - page 354 / 945
» Dynamic Architecture Extraction
Sort
View
VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
16 years 7 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...
VLSID
2004
IEEE
120views VLSI» more  VLSID 2004»
16 years 7 months ago
Dynamic Power Optimization of Interactive Systems
Abstract-- Power has become a major concern for mobile computing systems such as laptops and handhelds, on which a significant fraction of software usage is interactive instead of ...
Lin Zhong, Niraj K. Jha
GLVLSI
2009
IEEE
132views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Multicast routing with dynamic packet fragmentation
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper
168
Voted
IEEEPACT
2009
IEEE
16 years 1 months ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
CAISE
2009
Springer
16 years 1 months ago
Complexity Levels of Representing Dynamics in EA Planning
Abstract. Enterprise Architecture (EA) models provide information on the fundamental as-is structure of a company or governmental agency and thus serve as an informational basis fo...
Stephan Aier, Bettina Gleichauf, Jan Saat, Robert ...