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CODES
2005
IEEE
16 years 9 days ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
15 years 12 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
SAINT
2003
IEEE
15 years 12 months ago
Jini Meets UPnP: An Architecture for Jini/UPnP Interoperability
A service discovery framework provides a collection of protocols for developing dynamic client/server applications, allowing clients to find and use services without any previous ...
Jérémie Allard, V. Chinta, S. Gundal...
EUROPAR
2009
Springer
15 years 11 months ago
Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
Cédric Augonnet, Samuel Thibault, Raymond N...
WOTUG
2007
15 years 7 months ago
A Process-Oriented Architecture for Complex System Modelling
Abstract. A fine-grained massively-parallel process-oriented model of platelets (potentially artificial) within a blood vessel is presented. This is a CSP inspired design, expres...
Carl G. Ritson, Peter H. Welch