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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 3 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
SBCCI
2006
ACM
139views VLSI» more  SBCCI 2006»
16 years 15 days ago
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
Leandro Möller, Rafael Soares, Ewerson Carval...
ICPP
2008
IEEE
16 years 1 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
IFIP
2003
Springer
15 years 11 months ago
A Novel Energy Efficient Communication Architecture for Bluetooth Ad Hoc Networks
Bluetooth is a promising wireless technology aiming at supporting electronic devices to be instantly interconnected into short-range ad hoc networks. The Bluetooth medium access co...
Carlos de M. Cordeiro, Sachin Abhyankar, Dharma P....
HPCA
1998
IEEE
15 years 10 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...