Sciweavers

291 search results - page 37 / 59
» Dual-Processor Design of Energy Efficient Fault-Tolerant Sys...
Sort
View
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
16 years 6 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
EUROMICRO
2004
IEEE
15 years 9 months ago
Determination of Aggregation Points in Wireless Sensor Networks
A primary goal in the design of wireless sensor networks is lifetime maximization, constrained by the energy capacity of batteries. One well known method to reduce energy consumpt...
Utz Roedig, André M. Barroso, Cormac J. Sre...
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
16 years 2 days ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
15 years 11 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...
CODES
2004
IEEE
15 years 9 months ago
Dynamic overlay of scratchpad memory for energy minimization
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
Manish Verma, Lars Wehmeyer, Peter Marwedel