291 search results - page 35 / 59 » Dual-Processor Design of Energy Efficient Fault-Tolerant Sys... |
134
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
161
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HICSS
2009
IEEE
16 years 29 days ago
2009
IEEE
One of the major challenges of designing a dissemination protocol for Wireless Sensor Networks (WSNs) is energy efficiency. Flooding and SPIN, which are very well-known proactive ...
156
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ISLPED
2004
ACM
15 years 11 months ago
2004
ACM
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
195
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ASPLOS
2010
ACM
15 years 9 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
261
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GIS
2003
ACM
16 years 7 months ago
2003
ACM
For many applications with spatial data management such as Geographic Information Systems (GIS), block-oriented access over flash memory could introduce a significant number of no...