55 search results - page 4 / 11 » Double-via-driven standard cell library design |
153
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DATE
2006
IEEE
16 years 1 days ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
115
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ISQED
2005
IEEE
15 years 11 months ago
2005
IEEE
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...
148
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ITC
2000
IEEE
15 years 10 months ago
2000
IEEE
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
172
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...
160
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ASYNC
2007
IEEE
16 years 10 days ago
2007
IEEE
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...