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GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
15 years 11 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
HPCA
2000
IEEE
15 years 11 months ago
Impact of Heterogeneity on DSM Performance
This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
Renato J. O. Figueiredo, José A. B. Fortes
COLT
1999
Springer
15 years 10 months ago
Beating the Hold-Out: Bounds for K-fold and Progressive Cross-Validation
The empirical error on a test set, the hold-out estimate, often is a more reliable estimate of generalization error than the observed error on the training set, the training estim...
Avrim Blum, Adam Kalai, John Langford
ICPP
1998
IEEE
15 years 10 months ago
High-Level Information - An Approach for Integrating Front-End and Back-End Compilers
We propose a new universal High-Level Information (HLI) format to effectively integrate front-end and back-end compilers by passing front-end information to the back-end compiler....
Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia...