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DAC
1998
ACM
16 years 7 months ago
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
DAC
2001
ACM
16 years 7 months ago
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
Jafar Savoj, Behzad Razavi
DAC
2005
ACM
16 years 7 months ago
Effective bounding techniques for solving unate and binate covering problems
Covering problems arise in many areas of electronic design automation such as logic minimization and technology mapping. An exact solution can critically impact both size and perf...
Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
ICML
2009
IEEE
16 years 7 months ago
A simpler unified analysis of budget perceptrons
The kernel Perceptron is an appealing online learning algorithm that has a drawback: whenever it makes an error it must increase its support set, which slows training and testing ...
Ilya Sutskever
ICML
2007
IEEE
16 years 7 months ago
On one method of non-diagonal regularization in sparse Bayesian learning
In the paper we propose a new type of regularization procedure for training sparse Bayesian methods for classification. Transforming Hessian matrix of log-likelihood function to d...
Dmitry Kropotov, Dmitry Vetrov