Sciweavers

7379 search results - page 906 / 1476
» Distributed vector architectures
Sort
View
ICS
2009
Tsinghua U.
16 years 1 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
CSE
2009
IEEE
16 years 1 months ago
Implementing Social Norms Using Policies
—Multi-agent systems are difficult to develop. One reason for this is that agents are embedded in a society where all agents must agree to obey certain social norms in order for...
Robert Kremer
ICS
2007
Tsinghua U.
16 years 1 months ago
Scheduling FFT computation on SMP and multicore systems
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
Ayaz Ali, S. Lennart Johnsson, Jaspal Subhlok
ISW
2005
Springer
16 years 16 days ago
gore: Routing-Assisted Defense Against DDoS Attacks
Abstract. We present gore, a routing-assisted defense architecture against distributed denial of service (DDoS) attacks that provides guaranteed levels of access to a network under...
Stephen T. Chou, Angelos Stavrou, John Ioannidis, ...
PACS
2004
Springer
146views Hardware» more  PACS 2004»
16 years 12 days ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...