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IPPS
2006
IEEE
16 years 19 days ago
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
PDP
2005
IEEE
16 years 5 days ago
Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures
In this work we evaluate the implementation of a video encoder based on the 3D Wavelet Transform optimized for HyperThreading technology and SMPs. We design several implementation...
Ricardo Fernández, José M. Garc&iacu...
EUROPAR
2004
Springer
15 years 12 months ago
Targeting Heterogeneous Architectures in ASSIST: Experimental Results
Abstract. We describe how the ASSIST parallel programming environment can be used to run parallel programs on collections of heterogeneous workstations and evaluate the scalability...
Marco Aldinucci, Sonia Campa, Massimo Coppola, Sil...
IPPS
2003
IEEE
15 years 12 months ago
Architectural Frameworks for MPP Systems on a Chip
Advances in fabrication techniques are now enabling new hybrid CPU/FPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant perfor...
David L. Andrews, Douglas Niehaus
HICSS
1999
IEEE
121views Biometrics» more  HICSS 1999»
15 years 11 months ago
Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures
Distributed Shared Memory (DSM) combines the scalability of loosely coupled multicomputer systems with the ease of usability of tightly coupled multiprocessors, and allows transpa...
M. Rasit Eskicioglu, T. Anthony Marsland, Weiwu Hu...