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ICS
2003
Tsinghua U.
15 years 11 months ago
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
Power consumption is a critical issue in interconnection network design, driven by power-related design constraints, such as thermal and power delivery design. Usually, off-line w...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
CF
2010
ACM
15 years 11 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
IEEEPACT
2002
IEEE
15 years 11 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
IPPS
2002
IEEE
15 years 11 months ago
Implementing Associative Search and Responder Resolution
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
Meiduo Wu, Robert A. Walker, Jerry L. Potter
EUROPAR
2001
Springer
15 years 11 months ago
Building TMR-Based Reliable Servers Despite Bounded Input Lifetimes
This paper is on the construction of a server subsystem in a client/server system in an application context where the number of potential clients can be arbitrarily large. The imp...
Paul D. Ezhilchelvan, Jean-Michel Hélary, M...