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1999
Tsinghua U.
15 years 11 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
ICRA
1998
IEEE
132views Robotics» more  ICRA 1998»
15 years 11 months ago
A 3-D Self-Reconfigurable Structure
: A three-dimensional, self-reconfigurable structure is proposed. The structure is a fully distributed system composed of many identical 3-D units. Each unit has functions of chang...
Satoshi Murata, Haruhisa Kurokawa, Eiichi Yoshida,...
IPPS
1998
IEEE
15 years 11 months ago
Memory Hierarchy Management for Iterative Graph Structures
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
Ibraheem Al-Furaih, Sanjay Ranka
IPPS
1998
IEEE
15 years 11 months ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
IPPS
1998
IEEE
15 years 11 months ago
Predicting the Running Times of Parallel Programs by Simulation
Predicting the running time of a parallel program is useful for determining the optimal values for the parameters of the implementation and the optimal mapping of data on processo...
Radu Rugina, Klaus E. Schauser