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HPCA
2006
IEEE
16 years 7 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
HPCA
2006
IEEE
16 years 7 months ago
CMP design space exploration subject to physical constraints
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
Yingmin Li, Benjamin C. Lee, David Brooks, Zhigang...
HPCA
2003
IEEE
16 years 7 months ago
Hierarchical Backoff Locks for Nonuniform Communication Architectures
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...
Zoran Radovic, Erik Hagersten
HPCA
2002
IEEE
16 years 7 months ago
Quantifying Load Stream Behavior
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
Suleyman Sair, Timothy Sherwood, Brad Calder
HPCA
2001
IEEE
16 years 7 months ago
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers
We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops do not ...
Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alo...