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CF
2005
ACM
15 years 8 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
15 years 4 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
INFOCOM
2005
IEEE
16 years 3 days ago
Architecture and algorithms for an IEEE 802.11-based multi-channel wireless mesh network
— Even though multiple non-overlapped channels exist in the 2.4GHz and 5GHz spectrum, most IEEE 802.11-based multi-hop ad hoc networks today use only a single channel. As a resul...
Ashish Raniwala, Tzi-cker Chiueh
ICCS
2004
Springer
15 years 12 months ago
Complex Network of Earthquakes
Complex Network of Earthquakes Sumiyoshi Abe Institute of Physics, University of Tsukuba Ibaraki 3058571, Japan First, a brief discussion is made about a relevance of nonextensive...
Sumiyoshi Abe, Norikazu Suzuki
WCW
2004
Springer
15 years 12 months ago
ShortCuts: Using Soft State to Improve DHT Routing
Distributed hash tables are increasingly being proposed as the core substrate for content delivery applications in the Internet, such as cooperative Web caches, Web index and sear...
Kiran Tati, Geoffrey M. Voelker