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ICPP
2008
IEEE
16 years 29 days ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
ISCA
2006
IEEE
145views Hardware» more  ISCA 2006»
15 years 6 months ago
Techniques for Multicore Thermal Management: Classification and New Exploration
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
James Donald, Margaret Martonosi
HPCA
2012
IEEE
14 years 2 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
WDAG
2009
Springer
166views Algorithms» more  WDAG 2009»
16 years 1 months ago
New Bounds for the Controller Problem
The (M, W)-controller, originally studied by Afek, Awerbuch, Plotkin, and Saks, is a basic ted tool that provides an abstraction for managing the consumption of a global resource ...
Yuval Emek, Amos Korman
HPCA
2009
IEEE
16 years 7 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi