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180
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HPCA
2005
IEEE
16 years 7 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
200
Voted
IEEEPACT
2006
IEEE
16 years 27 days ago
Architectural support for operating system-driven CMP cache management
The role of the operating system (OS) in managing shared resources such as CPU time, memory, peripherals, and even energy is well motivated and understood [23]. Unfortunately, one...
Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
220
Voted
TDSC
2010
218views more  TDSC 2010»
15 years 5 months ago
Secure Data Objects Replication in Data Grid
—Secret sharing and erasure coding-based approaches have been used in distributed storage systems to ensure the confidentiality, integrity, and availability of critical informati...
Manghui Tu, Peng Li, I-Ling Yen, Bhavani M. Thurai...
163
Voted
CIMCA
2006
IEEE
16 years 28 days ago
Timed-MPSG: A Formal Model for Real-Time Shop Floor Controller
The MPSG (Message-based Part State Graph) model has been developed for the execution portion of shop-floor controllers that operate in a distributed and hierarchical control envir...
Devinder Thapa, Jaeil Park, Gi-Nam Wang, Dongmin S...
CONCUR
2000
Springer
15 years 11 months ago
Formal Models for Communication-Based Design
Concurrency is an essential element of abstract models for embedded systems. Correctness and e ciency of the design depend critically on the way concurrency is formalized and imple...
Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, L...