There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
This paper addresses the problem of stochastic task execution time estimation agnostic to the process distributions. The proposed method is orthogonal to the application structure ...
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
We consider the randomized consensus protocol of Aspnes and Herlihy for achieving agreement among N asynchronous processes that communicate via read/write shared registers. The alg...
Marta Z. Kwiatkowska, Gethin Norman, Roberto Segal...