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HPCA
2009
IEEE
16 years 1 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
SLIP
2009
ACM
16 years 25 days ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya...
IEEEPACT
2008
IEEE
16 years 22 days ago
Characterizing and modeling the behavior of context switch misses
One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very ...
Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abd...
ICS
2007
Tsinghua U.
16 years 14 days ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi
ICRA
2000
IEEE
163views Robotics» more  ICRA 2000»
15 years 10 months ago
The Anthropomorphic Biped Robot BIP2000
This paper describes the progress of the BIP2000 project. This project, in which four laboratories are involved for 4 years, as uimed at the realization of the lower part of an an...
Bernard Espiau, Philippe Sardain