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HPDC
2010
IEEE
15 years 7 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
CJ
2006
84views more  CJ 2006»
15 years 7 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
RSA
2000
170views more  RSA 2000»
15 years 7 months ago
Delayed path coupling and generating random permutations
We analyze various stochastic processes for generating permutations almost uniformly at random in distributed and parallel systems. All our protocols are simple, elegant and are b...
Artur Czumaj, Miroslaw Kutylowski
IPPS
2005
IEEE
16 years 25 days ago
Virtual Gateways in the DECOS Integrated Architecture
— The DECOS architecture aims at combining the advantages of federated and integrated systems. The DECOS architecture divides the overall system into a set of nearly-independent ...
Roman Obermaisser, Philipp Peti, Hermann Kopetz
SIGCOMM
2005
ACM
16 years 24 days ago
OpenDHT: a public DHT service and its uses
Large-scale distributed systems are hard to deploy, and distributed hash tables (DHTs) are no exception. To lower the barriers facing DHT-based applications, we have created a pub...
Sean C. Rhea, Brighten Godfrey, Brad Karp, John Ku...