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IPPS
2000
IEEE
15 years 12 months ago
Register Assignment for Software Pipelining with Partitioned Register Banks
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...
IPPS
2000
IEEE
15 years 12 months ago
Switch Scheduling in the Multimedia Router (MMR)
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
Damon S. Love, Sudhakar Yalamanchili, José ...
IPPS
2000
IEEE
15 years 12 months ago
Study of a Multilevel Approach to Partitioning for Parallel Logic Simulation
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
Swaminathan Subramanian, Dhananjai Madhava Rao, Ph...
IPPS
2000
IEEE
15 years 12 months ago
Monotonic Counters: A New Mechanism for Thread Synchronization
Only a handful of fundamental mechanisms for synchronizing the access of concurrent threads to shared memory are widely implemented and used. These include locks, condition variab...
John Thornley, K. Mani Chandy
ISADS
1999
IEEE
15 years 11 months ago
Fault Tolerance in Decentralized Systems
: In a decentralised system the problems of fault tolerance, and in particular error recovery, vary greatly depending on the design assumptions. For example, in a distributed datab...
Brian Randell