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IPPS
2006
IEEE
16 years 14 days ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
IPPS
2006
IEEE
16 years 14 days ago
Seekable sockets: a mechanism to reduce copy overheads in TCP-based messaging
This paper extends the traditional socket interface to TCP/IP communication with the ability to seek rather than simply receive data in order. Seeking on a TCP socket allows a use...
Chase Douglas, Vijay S. Pai
IPPS
2006
IEEE
16 years 14 days ago
Parallel morphological processing of hyperspectral image data on heterogeneous networks of computers
Recent advances in space and computer technologies are revolutionizing the way remotely sensed data is collected, managed and interpreted. The development of efficient techniques ...
Antonio J. Plaza
IPPS
2006
IEEE
16 years 14 days ago
A dependable infrastructure of the electric network for e-textiles
Electronic textiles, known as computational fabrics, offer an emerging method for constructing wearable and large area applications. Because e-textiles are battery-driven and faul...
Nenggan Zheng, Zhaohui Wu, Man Lin, Minde Zhao
IPPS
2006
IEEE
16 years 14 days ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....