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VLSID
2008
IEEE
95views VLSI» more  VLSID 2008»
16 years 8 months ago
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
Biswajit Ray, Santanu Mahapatra
VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
16 years 8 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
16 years 8 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
16 years 8 months ago
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, H...
SIGMOD
2002
ACM
187views Database» more  SIGMOD 2002»
16 years 7 months ago
A Conceptual Architecture for Semantic Web Enabled Web Services
Semantic Web Enabled Web Services (SWWS) will transform the web from a static collection of information into a distributed device of computation on the basis of Semantic Web techn...
Christoph Bussler, Dieter Fensel, Alexander Maedch...
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