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ECBS
2002
IEEE
81views Hardware» more  ECBS 2002»
15 years 11 months ago
Optimization of a Retargetable Functional Simulator for Embedded Processors
The objective of this research is to develop tools and methods for system-level optimization of embedded software that is executed on system-on-chip platforms. In particular, this...
Francesco Papariello, Gabriele Luculli
LCTRTS
2001
Springer
15 years 10 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
EUROMICRO
2000
IEEE
15 years 10 months ago
Behavioral Specification of a Circuit Using SyncCharts: A Case Study
In this paper we propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: “SyncCharts”. SyncCharts supp...
Charles André, Marie-Agnès Peraldi-F...
ASPDAC
2000
ACM
120views Hardware» more  ASPDAC 2000»
15 years 10 months ago
Data memory minimization by sharing large size buffers
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
Hyunok Oh, Soonhoi Ha
ASPDAC
1999
ACM
107views Hardware» more  ASPDAC 1999»
15 years 10 months ago
New Multilevel and Hierarchical Algorithms for Layout Density Control
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...